Senior Scientist System Design - Silicon Austria Labs GmbH

Farkas Kiss Endre legjobb állása Silicon Austria Labs GmbH

contact@silicon-austria.com

Bewerbung fur Senior Expert IT Support - Silicon Austria Labs GmbH

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Lieber Silicon Austria Labs GmbH!

Ich möchte mich bei Ihrem Unternehmen als Senior Scientist System Design - Silicon Austria Labs GmbH bewerben. 
Ich bin ein Fullstack-Entwickler, bei dem ich meine 10-jährige Erfahrung mit verschiedenen Technologien einsetzen kann.

Ich habe meinen Lebenslauf an diese E-Mail angehängt.

Wir freuen uns darauf, von Ihnen zu hören!


Endre Farkas Kiss "Sodika"
Java and PHP Fullstack Developer, Nudist, Vlogger

https://www.linkedin.com/in/farkas-kiss-63bb9210a
https://sodika.org

Álláshirdetés szövege

Deine Rolle im Team
Deliver complex digital IPs, meeting schedule, area, power, and performance targets.
Collaborate in developing precise design specifications for digital control blocks.
Implement FSM's and other control logic in System Verilog.
Collaborate with managers and program managers to track progress and gauge tapeout readiness.
Work with Digital Verification teams to create verification plans.
Work with silicon validation team in developing lab validation and qualification plans.
Commitment to writing publications and attendance on relevant conferences.
Leading research projects and participating in acquisition of industry projects and funding grants.

Technologien und Skills
TCL
Perl
Python
Cadence
Gauge
Synopsys
Verilog
MATLAB

Unsere Erwartungen an dich:
Qualifikationen
RTL design fundamentals (Verilog and System-Verilog).
Architecture exploration and micro-architecture development.
On Chip Infrastructure (AMBA/PCIe/USB/JTAG,NoC).
Static Timing Analysis tools.
Clock Domain Crossing.
Functional and formal Verification.
Scripting languages (Tcl, Python, Perl, MATLAB, Shell-scripting).
Excellent oral and written English skills, German is a plus.
Autonomous, well organized and enjoy working in a dynamic and multicultural team.

Erfahrung
Silicon development experience.
Digital IP design/integration experience.
Back-end tool experience (synthesis & Place and Route).
Experience with EDA tools (simulator/debug/synthesis/timing analysis/place&route) from major vendors (Synopsys/Cadence/Mentor).
Good experience in project management.

Ausbildung
PhD in Electrical Engineering with strong background in digital IC design + min. of 4 years of relevant working experience or MSc in relevant topic + min. 7 years of relevant working experience.

Benefits
Mitarbeiterprämie
Home Office
Essenszulage
Bonuszahlungen
Flexible Arbeitszeiten
Frisches Obst
Kaffee, Tee o. Ä